A Novel Hierarchical Test Generation Method for Processors

Raghuram S. Tupuri Advanced Processor Development Advanced Micro devices Austin TX 78741 Jacob A. Abraham Computer Engineering Research Center University of Texas at Austin Austin TX 78752 same coverage is obtained. Figure 1 illustrates the proposed hierarchical test generation process using a commercially available test generator. This paper describes a novel method for hierarchical functional test generation for processors. This method targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Since the commercial tools are unable to deal with the entire design, functional constraints are first extracted for the module. The extracted constraints are described in VerilogNHDL and synthesized to the gate level. Then a commercial sequential ATPG is used to generate module level test vectors for faults within the module. Finally, these module level vectors are translated to processor level functional vectors and fault simulated to verify that the same coverage is obtained. Applying the technique to a benchmark processor design, we were able to obtain a test efficiency for the embedded ALU of the processor which was extremely close to what the commercial ATPG could do with complete access to the module.